1. Field of the Invention:
The present invention relates to the speed control of passenger vehicles, such as mass transit vehicles or the like, and including the decoding of wayside-provided speed codes for vehicle speed control and speed maintenance purposes while the vehicle is moving along a roadway track.
2. Description of the Prior Art:
It is known in the prior art to provide a checked redundancy speed error determination as disclosed in U.S. Pat. No. 3,749,994 of T. C. Matty. It is also known in the prior art to individually decode the ones data and the zeros data of an input speed command from the roadway track, and then to compare the ones data with the zeros data to detect any discrepancy as disclosed in U.S. Pat. No. 4,015,082 of T. C. Matty et al.
A signal is provided for each pair of channels, which determines the operation of the propulsion and brake controller and in addition is fed back to the integrity check operations of the other pairs of channels. An underspeed operation enable signal is provided by each pair of channels to determine the operation of the propulsion and brake controller, and in addition is fed back to the integrity check operation of the other pairs of channels.
A general description of the microprocessors and the related peripheral devices as shown in FIG. 4 of the drawings is provided in the Intel Component Data Catalog currently available from Intel Corporation, Santa Clara, Calif. 95051.